论文标题
与中间QUTRIT辅助栅极分解的电路的容错性
On Fault Tolerance of Circuits with Intermediate Qutrit-assisted Gate Decomposition
论文作者
论文摘要
已经提出了一些中间QUTRIT进行有效分解3 Quit统一门的,以获得分解电路深度的指数降低。中间QUTRIT意味着在特定执行周期中将量子量作为Qutrit操作。这种方法主要用于NISQ时代,仅在计算过程中需要访问状态$ \ ket {2} $时,才能将量子视为Qutrit。在本文中,我们研究了在这种分解中包括容忍度的挑战。我们首先表明,任何需要在电路中的任何点访问状态$ \ ket {2} $的Qubit,都必须使用QUTRIT量子误差校正代码(QECC)编码。由于Qutrits比Qubits嘈杂,因此前者需要更高的串联才能获得特定的准确性,而不是仅量子分解。接下来,我们通过分析得出(i)Qubit-Qutrit和仅量子分解所需的串联级别数量作为误差概率的函数,以及(ii)Qubit-Qutrit分解的标准会导致与Qubit Onally分解相比,导致栅极计数较低的栅极计数。我们提出了这两种类型的分解的数值结果,并通过考虑量子硬件 - 噪声和非转换实现的量子加法器的示例示例的示例电路,并获得了量子加法器的示例示例的数值结果。
The use of a few intermediate qutrits for efficient decomposition of 3-qubit unitary gates has been proposed, to obtain an exponential reduction in the depth of the decomposed circuit. An intermediate qutrit implies that a qubit is operated as a qutrit in a particular execution cycle. This method, primarily for the NISQ era, treats a qubit as a qutrit only for the duration when it requires access to the state $\ket{2}$ during the computation. In this article, we study the challenges of including fault-tolerance in such a decomposition. We first show that any qubit that requires access to the state $\ket{2}$ at any point in the circuit, must be encoded using a qutrit quantum error correcting code (QECC), thus resulting in a circuit with both qubits and qutrits at the outset. Since qutrits are noisier than qubits, the former is expected to require higher levels of concatenation to achieve a particular accuracy than that for qubit-only decomposition. Next, we derive analytically (i) the number of levels of concatenation required for qubit-qutrit and qubit-only decompositions as a function of the probability of error, and (ii) the criterion for which qubit-qutrit decomposition leads to a lower gate count than qubit-only decomposition. We present numerical results for these two types of decomposition and obtain the situation where qubit-qutrit decomposition excels for the example circuit of the quantum adder by considering different values for quantum hardware-noise and non-transversal implementation of the 2-controlled ternary CNOT gate.