论文标题
带有检查节点的可变节点设计，利用2位LDPC解码
A Variable Node Design with Check Node Aware Quantization Leveraging 2-Bit LDPC Decoding
论文作者
论文摘要
为了改善LDPC代码的粗量化解码，我们建议对变量节点更新的检查节点意识到。与以前的工作相反，我们优化了变量节点，以明确地最大化保留在check-to-to-to-to-to-to-to-to-to-to-to-car-car-to-check节点消息中的相互信息。扩展优化导致在变量节点处的压缩操作的明显不同。常规的LDPC代码的仿真结果确认，检查节点意识到的设计，尤其是对于使用2次或3位消息的非常粗糙的量化，可实现高达0.2 dB的性能增长 - 而无需其他硬件成本。我们还表明，2位消息解决方案可以非常有效地实现检查节点更新，该更新仅需要3位检查节点的晶体管计数的2/9，并将信号传播延迟降低4。
For improving coarsely quantized decoding of LDPC codes, we propose a check node aware design of the variable node update. In contrast to previous works, we optimize the variable node to explicitly maximize the mutual information preserved in the check-to-variable instead of the variable-to-check node messages. The extended optimization leads to a significantly different solution for the compression operation at the variable node. Simulation results for regular LDPC codes confirm that the check node aware design, especially for very coarse quantization with 2- or 3-bit messages, achieves performance gains of up to 0.2 dB - without additional hardware costs. We also show that the 2-bit message resolution enables a very efficient implementation of the check node update, which requires only 2/9 of the 3-bit check node's transistor count and reduces the signal propagation delay by a factor of 4.
