论文标题

将快速本地解码器与电路级噪声下的全球解码器相结合的技术

Techniques for combining fast local decoders with global decoders under circuit-level noise

论文作者

Chamberland, Christopher, Goncalves, Luis, Sivarajah, Prasahnt, Peterson, Eric, Grimberg, Sebastian

论文摘要

在容忍故障的量子计算机上实现算法将需要快速解码吞吐量和延迟时间,以防止大门应用程序之间的缓冲时间呈指数增加。在这项工作中,我们首先量化这些要求。然后,我们使用三维卷积介绍了当地神经网络(NN)解码器的构建。这些本地解码器适用于电路级噪声,并可以应用于任意大小的表面代码量。它们的应用消除了由于一定数量的故障而引起的错误,这大大降低了综合征密度。然后,由于综合征密度降低,剩余的错误可以通过全球解码器(例如Blossom或Union发现)纠正,其实施大大加速。但是,在电路级设置中,本地解码器应用的校正引入了许多垂直的突出显示顶点。为了在垂直对的情况下获得低综合征密度,我们考虑了执行综合征崩溃的策略,该策略可以去除许多垂直对并减小全局解码器使用的解码图的大小。我们还考虑了执行垂直清理的策略,该策略包括在实施全球解码器之前删除所有本地垂直对。最后,我们估计在现场可编程门阵列(FPGA)上实施本地解码器的成本。

Implementing algorithms on a fault-tolerant quantum computer will require fast decoding throughput and latency times to prevent an exponential increase in buffer times between the applications of gates. In this work we begin by quantifying these requirements. We then introduce the construction of local neural network (NN) decoders using three-dimensional convolutions. These local decoders are adapted to circuit-level noise and can be applied to surface code volumes of arbitrary size. Their application removes errors arising from a certain number of faults, which serves to substantially reduce the syndrome density. Remaining errors can then be corrected by a global decoder, such as Blossom or Union Find, with their implementation significantly accelerated due to the reduced syndrome density. However, in the circuit-level setting, the corrections applied by the local decoder introduce many vertical pairs of highlighted vertices. To obtain a low syndrome density in the presence of vertical pairs, we consider a strategy of performing a syndrome collapse which removes many vertical pairs and reduces the size of the decoding graph used by the global decoder. We also consider a strategy of performing a vertical cleanup, which consists of removing all local vertical pairs prior to implementing the global decoder. Lastly, we estimate the cost of implementing our local decoders on Field Programmable Gate Arrays (FPGAs).

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