论文标题
SOC FPGA实施的无人机自动着陆算法的硬件式仿真
Hardware-in-the-loop simulation of a UAV autonomous landing algorithm implemented in SoC FPGA
论文作者
论文摘要
本文介绍了在异质SOC FPGA计算平台上实施的无人机（UAV）控制算法的硬件（HIL）模拟系统。使用了在PC上运行的Airsim模拟器和带有来自AMD Xilinx的Zynq Soc芯片的Arty Z7开发板。通信是通过串行USB链接进行的。选择了在特殊标记的着陆条上的自主降落申请作为案例研究。在Zynq SoC平台上实施了着陆点检测算法。这样可以实时处理1280 x 720 @ 60 fps视频流。执行的测试表明，该系统正常工作，并且没有可能对控制的稳定性产生负面影响。所提出的概念的特征是相对简单和实施成本较低。同时，它可以应用于在嵌入式平台上实现的无人机测试各种类型的高级感知和控制算法。我们提供在GitHub上开发的代码，该代码包括在PC上运行的Python脚本和在Arty Z7上运行的C代码。
This paper presents a system for hardware-in-the-loop (HiL) simulation of unmanned aerial vehicle (UAV) control algorithms implemented on a heterogeneous SoC FPGA computing platforms. The AirSim simulator running on a PC and an Arty Z7 development board with a Zynq SoC chip from AMD Xilinx were used. Communication was carried out via a serial USB link. An application for autonomous landing on a specially marked landing strip was selected as a case study. A landing site detection algorithm was implemented on the Zynq SoC platform. This allowed processing a 1280 x 720 @ 60 fps video stream in real time. Performed tests showed that the system works correctly and there are no delays that could negatively affect the stability of the control. The proposed concept is characterised by relative simplicity and low implementation cost. At the same time, it can be applied to test various types of high-level perception and control algorithms for UAV implemented on embedded platforms. We provide the code developed on GitHub, which includes both Python scripts running on the PC and C code running on Arty Z7.
