论文标题
与RISC-V和ESP启用异质的多项SOC研究
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP
论文作者
论文摘要
异质，多层SOC架构是当今计算景观的关键组成部分。但是，支持不断增加的异质性和多核执行是重大的设计挑战。同时，不断增长的RISC-V和开源硬件（OSH）运动导致了大量的开源RISC-V处理器实现。但是，将这些处理器核心集成的开源SOC设计平台较少。我们为开源SOC设计平台ESP提供了修改，以通过RISC-V CVA6处理器启用多项执行。我们的实现是模块化的，并且基于标准化界面。这些属性简化了新内核的整合。我们的修改使基于RISC-V的SOCS使用ESP设计为FPGA启动Linux SMP并执行多线程应用程序。加上ESP的强调以加速器为中心的架构，我们的贡献使得无缝设计了各种异质，多核心SOC。
Heterogeneous, multicore SoC architectures are a critical component of today's computing landscape. However, supporting both increasing heterogeneity and multicore execution are significant design challenges. Meanwhile, the growing RISC-V and open-source hardware (OSH) movements have resulted in an increased number of open-source RISC-V processor implementations; however, there are fewer open source SoC design platforms that integrate these processor cores. We present modifications to ESP, an open-source SoC design platform, to enable multicore execution with the RISC-V CVA6 processor. Our implementation is modular and based on standardized interfaces. These properties simplify the integration of new cores. Our modifications enable RISC-V-based SoCs designed with ESP for FPGA to boot Linux SMP and execute multithreaded applications. Coupled with ESP's emphasis on accelerator-centric architectures, our contributions enable the seamless design of a wide range of heterogeneous, multicore SoCs.
