论文标题
使用共振能量回收在14 nm finfet时钟中使用谐振能量回收
Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks
论文作者
论文摘要
随着对高性能微处理器的需求增加，电路复杂性和数据传输速率增加，从而导致更高的功耗。我们提出了一种时钟体系结构，该架构使用系列LC共振和电感器匹配技术来解决此瓶颈。通过采用脉冲共振，解散的开关功率被回收。电感器匹配技术有助于减少偏斜，从而增加了时钟网络的稳健性。与传统的基于基于触发器的CMOS架构相比，这种新的共振架构可节省超过43％的功率，而91％的偏向为1--5 GHz的范围。
As the demand for high-performance microprocessors increases, the circuit complexity and the rate of data transfer increases resulting in higher power consumption. We propose a clocking architecture that uses a series LC resonance and inductor matching technique to address this bottleneck. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor matching technique aids in reducing the skew, increasing the robustness of the clock network. This new resonant architecture saves over 43% power and 91% skew clocking a range of 1--5 GHz, compared to a conventional primary-secondary flip-flop-based CMOS architecture.
