论文标题
有效的后处理器，用于改善LDPC代码的错误校正性能
Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes
论文作者
论文摘要
与迭代解码器相关的误差地板现象是对低密度平等检查（LDPC）代码应用的最重要局限性之一。已经提出了从代码设计到解码器实施的各种技术来解决错误地板问题，其中后处理器已证明既有效又对实施友好。在这项工作中，我们从模拟退火中汲取灵感，使用三种方法概括后处理器设计：淬火，扩展加热和聚焦加热，每个方法都针对不同的误差结构。证明所得的后处理器可将两个结构化代码示例的误差地板降低两个数量级，即（2209，1978）阵列LDPC代码和A（1944，1620）由IEEE 802.11N标准使用的（1944，1620）LDPC代码。后处理器可以将其集成到具有最小开销的信念形成解码器中。后处理器设计同样适用于其他结构化的LDPC代码。
The error floor phenomenon, associated with iterative decoders, is one of the most significant limitations to the applications of low-density parity-check (LDPC) codes. A variety of techniques from code design to decoder implementation have been proposed to address the error floor problem, among which post-processors have shown to be both effective and implementation-friendly. In this work, we take the inspiration from simulated annealing to generalize the post-processor design using three methods: quenching, extended heating, and focused heating, each of which targets a different error structure. The resulting post-processor is demonstrated to lower the error floors by two orders of magnitude for two structured code examples, a (2209, 1978) array LDPC code, and a (1944, 1620) LDPC code used by the IEEE 802.11n standard. The post-processor can be integrated to a belief-propagation decoder with minimal overhead. The post-processor design is equally applicable to other structured LDPC codes.
