论文标题
一个基于2T电压参考的当前参考的家族：0.18- $μ$ m的演示为0.1-na PTAT和1.1- $ $ $ a CWT 38-PPM/$^\ circ $ c Designs
A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$μ$m with 0.1-nA PTAT and 1.1-$μ$A CWT 38-ppm/$^\circ$C Designs
论文作者
论文摘要
电流和电压引用对过程，电压和温度（PVT）变化的鲁棒性对于在实际条件下集成电路的运行至关重要。但是，尽管最近的电压参考可以通过少数晶体管满足这些要求中的大多数，但是当前的参考文献仍然相当复杂，需要大量的设计时间和硅区域。在本文中，我们介绍了一个简单的电流引用家族，该引用由两轨（2T）超低功率电压参考组成，并通过单个晶体管缓冲到电压到电流转换器上。在0.18- $ $ $ m部分的部分硅（SOI）技术中制造了两种拓扑结构，并在10个模具上进行了测量。首先，7T Na范围比例比例的温度（PTAT）参考，用于恒定的参考 - $ g_m $偏向亚阈值操作放大器的偏置显示0.096-Na电流，线敏感性（LS）为1.48％/v，温度系数（TC）为0.75％/$ $^$^$^$^$^$^$^$^$^$^convientive $^$^cirdime $ c。 1.66％。然后，带有（无用）TC校准的两个4T+1R $ $ $ a量量 - 温度（CWT）引用（cwt）参考（分别为0.21-％/v（分别为0.99- $ $ $ a）电流为0.21-％/v（ress。0.20-％/v），ls，38-v），38-pppm/$ $ $ c（counc） 290-PPM/$^\ CIRC $ C）TC和0.87-％（分别为0.65-％）$（σ/μ）$。此外，通过Layout后模拟讨论和验证了对普通缩放CMOS技术的可移植性，例如65 nm的体积和28 nm完全消耗的SOI。
The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18-$μ$m partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant-$g_m$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/$^\circ$C, and a variability $(σ/μ)$ of 1.66 %. Then, two 4T+1R $μ$A-range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09-$μ$A (resp. 0.99-$μ$A) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/$^\circ$C (resp. 290-ppm/$^\circ$C) TC, and a 0.87-% (resp. 0.65-%) $(σ/μ)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations.
