论文标题

基于FPGA-TDC的时间间隔的模拟数字转换调制器的设计

The design of a time-interleaved analog-digital conversion modulator based on FPGA-TDC for PET application

论文作者

Ma, Cong, Wang, Wubin, Zhao, Xiaokun, Yu, Li, Wu, Guocheng

论文摘要

用于高分辨率时间和能量测量的基于全场的可编程栅极阵列(FPGA)数字化处理器是正电子发射计算机断层扫描(PET)检测器中读出电子产品的有吸引力的低成本解决方案。近年来,基于FPGA的时数转换器(FPGA-TDC)已被广泛用于商用宠物扫描仪的时间测量。然而,对于能量测量,很少有关于基于FPGA的,较大的动态范围和高分辨率替代方案的商业模拟数字转换器(ADC)的研究。我们以前的研究介绍了基于25 ms/s FPGA-TDC的自由运行ADC(FPGA-ADC),并成功地将其用于宠物探测器的读取电子设备。在这项进行中的研究中,通过时间间隔策略,提出了50 ms/s的FPGA-ADC。只有两个外芯片电阻,在Xilinx Kintex-7 FPGA上都可以实现A/D转换和能量测量。因此,此方法具有很大的优势,无效系统集成。还提出了初始性能测试,我们希望它可以使我们有可能将来为PET开发新的仅FPGA前端数字化器。

Fully Field Programmable Gate Array (FPGA)based digitizer for high-resolution time and energy measurement is an attractive low cost solution for the readout electronics in positron emission computed tomography (PET)detector. In recent years, the FPGA based time-digital converter (FPGA-TDC) has been widely used for time measurement in the commercial PET scanners. Yet, for the energy measurement, few studies have been reported on a fully FPGA based, large dynamic range and high resolution alternative to the commercial analog-digital converter (ADC). Our previous research presents a 25 Ms/s FPGA-TDC based free-running ADC (FPGA-ADC), and successfully employed it in the readout electronics for PET detector. In this work-in-progress study, by means of the time-interleaved strategy, a 50 Ms/s FPGA-ADC is presented. With only two off-chip resistors, both the A/D conversion and energy measurement are achieved on a Xilinx Kintex-7 FPGA. Therefore, this method has great advantages inimproving system integration. Initial performance tests are also presented, and we hope it can give us a possibility to develop a new FPGA-only front-end digitizer for PET in future.

扫码加入交流群

加入微信交流群

微信交流群二维码

扫码加入学术交流群,获取更多资源