论文标题
基于压缩的芯片 - 多层处理器的节能非均匀级别缓存
Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression
论文作者
论文摘要
随着技术规模，CHIP-Multiprocessors（CMP）中的高速缓存系统的大小已大大增加，以有效地存储并操纵大量数据，并减少核心和离芯片内存访问之间的差距。对于未来的CMP架构，最近引入了3D LLC的3D堆叠，以应对2D集成和内存墙的性能挑战的新方法。但是，SRAM LLC的3D设计使热问题更加严重。因此，由于密集整合，它比传统的SRAM高速缓存体系结构相比，它会产生更多的泄漏能耗。在本文中，我们提出了两种不同的体系结构，以利用数据压缩以减少LLC和3D-ICS中互连的能量。
With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance challenges of 2D integration and the memory wall. However, the 3D design of SRAM LLCs has made the thermal problem even more severe. It, therefore, incurs more leakage energy consumption than conventional SRAM cache architectures in 2Ds due to dense integration. In this paper, we propose two different architectures that exploit the data compression to reduce the energy of LLC and interconnects in 3D-ICs.
