论文标题
3D-ICS对DNN-ACCELERATOR的架构，数据流和物理设计含义
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
论文作者
论文摘要
对深神经网络（DNN）对更高计算能力的永恒需求推动了并行计算体系结构的发展。 3D集成（其中芯片是集成并垂直连接的）可以进一步提高性能，因为它引入了另一个空间并行性。因此，我们分析了此类3D-DNN-加速器的数据流，性能，面积，功率和温度。将单片和基于TSV的堆叠3D-ICS与2D-ICS进行比较。我们确定有效3D-IC的工作负载属性和架构参数，并达到9.14倍3D与2D的速度。我们讨论区域绩效的权衡。我们证明了适用性，因为3D-IC汲取了与2D-IC相似的功率，而不是热限制的。
The everlasting demand for higher computing power for deep neural networks (DNNs) drives the development of parallel computing architectures. 3D integration, in which chips are integrated and connected vertically, can further increase performance because it introduces another level of spatial parallelism. Therefore, we analyze dataflows, performance, area, power and temperature of such 3D-DNN-accelerators. Monolithic and TSV-based stacked 3D-ICs are compared against 2D-ICs. We identify workload properties and architectural parameters for efficient 3D-ICs and achieve up to 9.14x speedup of 3D vs. 2D. We discuss area-performance trade-offs. We demonstrate applicability as the 3D-IC draws similar power as 2D-ICs and is not thermal limited.
