论文标题
用于极化调整后的卷积（PAC）代码的FANO解码器的硬件实现
Hardware Implementation of Fano Decoder for Polarization-adjusted Convolutional (PAC) Codes
论文作者
论文摘要
该简介提出了一种硬件实现体系结构，用于对极化调整后的卷积（PAC）代码的FANO解码。该架构使用特定于PAC代码的新型分支度量单元。提出的解码器在FPGA上进行了测试，并使用TSMC 28 nm 0.72 V库对其性能进行了评估。解码器可以以500 MHz的速度计时，并在3.5 dB信噪比的平均信息吞吐量为38 Mb/s，块长度为128，代码速率为1/2。
This brief proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture uses a novel branch metric unit specific to PAC codes. The proposed decoder is tested on FPGA, and its performance is evaluated on ASIC using TSMC 28 nm 0.72 V library. The decoder can be clocked at 500 MHz and reach an average information throughput of 38 Mb/s at 3.5 dB signal-to-noise ratio for a block length of 128 and a code rate of 1/2.
