论文标题
基于楼梯矩阵的FPGA实现大量MIMO检测
FPGA Implementation of Stair Matrix based Massive MIMO Detection
论文作者
论文摘要
基于近似矩阵反转的方法被广泛用于接收到的符号矢量检测的线性大量多输入多输出（MIMO）。此类探测器通常利用大型MIMO系统的对角线占主导地位矩阵。可以利用楼梯基质来改善大型MIMO检测器的误差性能，而不是对角线矩阵。在本文中，我们介绍了基于楼梯矩阵的迭代检测算法的非常大规模的集成（VLSI）体系结构和现场可编程栅极阵列（FPGA）实现。该体系结构支持一个基站，具有128个天线，8个具有单个天线的用户和256个正交振幅调制（QAM）。基于楼梯基质的检测器可以提供142.34 Mbps的数据速率，并在Xilinx VirTex-7 FPGA中达到258 MHz的时钟频率。比大多数当代大型MIMO探测器，检测器提供了出色的误差性能和更高的尺度吞吐量。
Approximate matrix inversion based methods is widely used for linear massive multiple-input multiple-output (MIMO) received symbol vector detection. Such detectors typically utilize the diagonally dominant channel matrix of a massive MIMO system. Instead of diagonal matrix, a stair matrix can be utilized to improve the error-rate performance of a massive MIMO detector. In this paper, we present very large-scale integration (VLSI) architecture and field programmable gate array (FPGA) implementation of a stair matrix based iterative detection algorithm. The architecture supports a base station with 128 antennas, 8 users with single antenna, and 256 quadrature amplitude modulation (QAM). The stair matrix based detector can deliver a 142.34 Mbps data rate and reach a clock frequency of 258 MHz in a Xilinx Virtex-7 FPGA. The detector provides superior error-rate performance and higher scaled throughput than most contemporary massive MIMO detectors.
