论文标题

大量MIMO OFDM中1位数据检测的算法和VLSI设计

Algorithm and VLSI Design for 1-bit Data Detection in Massive MIMO-OFDM

论文作者

Mirfarshbafan, Seyed Hadi, Shabany, Mahdi, Nezamalhosseini, Seyed Alireza, Studer, Christoph

论文摘要

在全数字大规模多输入多输出(MIMO)基座的射频(RF)链中使用低分辨率数据转换器有望大大降低功耗,硬件成本和互连带宽。我们提出了一种量化的数据检测算法,该算法减轻了1位量化大规模的模拟物频率分割多路复用(OFDM)系统的性能损失。由于系统性能在很大程度上取决于通道估计的质量,因此我们还开发了一种基于提出的数据检测算法的非线性1位通道估计算法。我们表明,所提出的算法在位错误率方面显着超过了线性数据检测器和通道估计器。对于提出的非线性数据检测算法,我们开发了非常大的集成(VLSI)体系结构,并在Xilinx virtex-7现场可编程门阵列(FPGA)上进行当前的实现结果。据我们所知,我们的实施结果是第一个用于1位大规模的MU-MIMO-OFDM系统的结果,并且相对于针对具有高分辨率数据转换器的系统设计的最先进的线性数据检测器,表现出可比的硬件效率,同时达到较低的位误差率。

The use of low-resolution data converters in the radio-frequency (RF) chains of all-digital massive multiple-input multiple-output (MIMO) basestations promises significant reductions in power consumption, hardware costs, and interconnect bandwidth. We propose a quantization-aware data-detection algorithm which mitigates the performance loss of 1-bit quantized massive MIMO orthogonal frequency-division multiplexing (OFDM) systems. Since the system performance heavily depends on the quality of channel estimates, we also develop a nonlinear 1-bit channel estimation algorithm that builds upon the proposed data detection algorithm. We show that the proposed algorithms significantly outperform linear data detectors and channel estimators in terms of bit error rate. For the proposed nonlinear data detection algorithm, we develop a very large scale integration (VLSI) architecture and present implementation results on a Xilinx Virtex-7 field programmable gate array (FPGA). Our implementation results are, to the best of our knowledge, the first for 1-bit massive MU-MIMO-OFDM systems and demonstrate comparable hardware efficiency with respect to state-of-the-art linear data detectors designed for systems with high-resolution data converters, while achieving lower bit error rate.

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