论文标题
负电容启用FinFet缩放超过3NM节点
Negative Capacitance Enables FinFET Scaling Beyond 3nm Node
论文作者
论文摘要
通过TCAD进行了负电容FinFET（NC-FINFET）的缩放缩放的全面研究。我们表明，NC-FINFET可以缩放到“ 2.1nm节点”和几乎“ 1.5nm节点”，该节点是在行业“ 3NM节点”之后出现的两个节点，该节点具有16NM LG，是国际设备和系统的国际路线图（IRDS）的最后一个FinFet节点。此外，对于中间节点，NC-FINFET可以在目标beating VDD的IRDS离子和IOFF目标。负电容的好处（NC）包括改进的子阈值坡度（SS），排水引起的屏障降低（DIBL），VT滚动，ID上的跨导率（GM/ID）（GM/ID），ID（GD/ID）的输出电导（GD/ID）和较低的VDD。可以通过改善铁电（Fe）和介电（DE）之间的电容匹配来实现进一步的缩放。
A comprehensive study of the scaling of negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that the NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm node" that comes two nodes after the industry "3nm node," which has 16nm Lg and is the last FinFET node according to the International Roadmap for Devices and Systems (IRDS). In addition, for the intervening nodes, NC-FinFET can meet IRDS Ion and Ioff target at target-beating VDD. The benefits of negative capacitance (NC) include improved subthreshold slope (SS), drain-induced barrier lowering (DIBL), Vt roll-off, transconductance over Id (Gm/Id), output conductance over Id (Gd/Id), and lower VDD. Further scaling may be achieved by improving capacitance matching between ferroelectric (FE) and dielectric (DE).
