论文标题
适应频率调整的机器学习管道阶段
A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment
论文作者
论文摘要
提出了一个机器学习（ML）设计框架，以根据单个说明的传播延迟来自适应调整时钟频率。训练了随机森林模型，以实时对传播延迟进行分类，利用当前的操作类型，当前操作数和计算历史记录为ML特征。训练有素的模型是在Verilog中实现的，作为基线处理器中的附加管道阶段。在45 nm CMOS技术中，在栅极水平上对修饰系统进行了实验测试，其加速度为70％，通过粗粒度的ML分类为30％的能量降低30％。表现出89％的加速度，其粒度更高，能源消耗降低了15.5％。
A machine learning (ML) design framework is proposed for adaptively adjusting clock frequency based on propagation delay of individual instructions. A random forest model is trained to classify propagation delays in real time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within a baseline processor. The modified system is experimentally tested at the gate level in 45 nm CMOS technology, exhibiting a speedup of 70% and energy reduction of 30% with coarse-grained ML classification. A speedup of 89% is demonstrated with finer granularities with 15.5% reduction in energy consumption.
