论文标题
基于香料电路级别的香料模型对负电容垂直纳米线FET的调查
The Investigation of Negative Capacitance Vertical Nanowire FETs Based on SPICE Model at Device-Circuit Level
论文作者
论文摘要
在这项研究中，提出了基于BSIM-CMG模型和Landau-Khalatnikov（LK）方程的负电容垂直纳米线磁场extistor（NC VNW-FET）的香料模型。受到短门长度的局限性，缺乏用于高性能NC VNW-FET的可控和集成结构。在Sub-3nm节点上提出了一种新的NC VNW-FETS结构。此外，为了理解和改善NC VNW-FET，S形偏振电压曲线（S-Curve）分为四个区域，并提出了一些新的设计规则。通过使用SPICE模型，实现了设备电路合作式化。研究了栅极工作函数（WF）和NC的共同设计。模拟了一个环振荡器来分析电路能量延迟，并表明可以实现低电源电压下的NC VNW-FET的大量能量降低，高达88％。这项研究提供了一种可靠的方法来分析基于NC的设备和电路的性能，并揭示了NC VNW-FETS在低功率应用中的潜力。
In this study, a SPICE model for negative capacitance vertical nanowire field-effect-transistor (NC VNW-FET) based on BSIM-CMG model and Landau-Khalatnikov (LK) equation was presented. Suffering from the limitation of short gate length there is lack of controllable and integrative structures for high performance NC VNW-FETs. A new kind of structure was proposed for NC VNW-FETs at sub-3nm node. Moreover, in order to understand and improve NC VNW-FETs, the S-shaped polarization-voltage curve (S-curve) was divided into four regions and some new design rules were proposed. By using the SPICE model, device-circuit co-optimization was implemented. The co-design of gate work function (WF) and NC was investigated. A ring oscillator was simulated to analyze the circuit energy-delay, and it shown that significant energy reduction, up to 88%, at iso-delay for NC VNW-FETs at low supply voltage can be achieved. This study gives a credible method to analysis the performance of NC based devices and circuits and reveals the potential of NC VNW-FETs in low-power applications.
